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description the CXP81952/81960 is a cmos 8-bit micro- computer which consists of a/d converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, pwm generator, pwm for tuner, 32khz timer/event counter, remote control receiving circuit, general purpose prescaler, and external signal, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also the CXP81952/81960 provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32khz operation. features a wide instruction set (213 instructions) which cover various types of data ?16-bit operation/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation 122s at 32khz operation incorporated rom capacity 52k bytes (CXP81952), 60k bytes (cxp81960) incorporated ram capacity 2048 bytes peripheral functions ?a/d converter 8-bit, 12-channel, successive approximation system (conversion time 20.0s/16mhz) ?serial interface incorporated buffer ram (1 to 32 bytes auto transfer) 1-channel incorporated 8-bit and 8-stage fifo for data (1 to 8 bytes auto transfer) 1-channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32khz timer/counter ?high precision timing pattern generator ppg 19-pin 32-stage programmable rtg 5-pin 2-channel ?pwm/da gate output pwm 12-bit, 2-channel (repetitive frequency 62khz/16mhz) da gate pulse output 13-bit, 4-channel ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14-bit, 1-channel ?remote control receiving circuit 8-bit pulse measurement counter with on-chip, 6-stage fifo ?general purpose prescaler 7-bit (pg5 input frequency divided, frc capture possible) interruption 20 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp piggyback/evaluation chip cxp81900 100-pin ceramic qfp/lqfp structure silicon gate cmos ic ?1 CXP81952/81960 e95110-st cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (piastic) 100 pin lqfp (piastic)
?2 CXP81952/81960 pi6/so1 a pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe1 pe2 to pe7 pf0 to pf3 pf4 to pf7 pg0 to pg7 pi1 to pi7 pj0 to pj7 vss v dd mp rst xtal extal clock generator/ system control ram 2048 bytes spc700 cpu core rom 52k/60k bytes interrupt controller 2 2 32khz timer/counter fifo frc capture unit programmable pattern generator ram 2 5 19 avss av ref av dd a/d converter serial interface unit (ch0) ram 8 bit timer/counter 0 8 bit timer 1 14 bit pwm generator 12 bit pwm generator ch0 2 2 12 bit pwm generator ch1 4 pe7/dab1 pe5/daa1 pe3/pwm1 pe6/dab0 pe4/daa0 pe2/pwm0 pi2/pwm pi1/rmc pg7/exi1 pg6/exi0 pi3/to pe1/ec pi5/sck1 pi7/si1 sck0 so0 si0 cs0 pf0/an4 to pf7/an11 an0 to an3 realtime pulse generator pe1/int2 pe0/int0 pi4/int1/nmi 12 8 port a 8 port b 8 port c 8 port d 6 2 port e 4 4 port f 8 port g 8 port h 7 port i ph0 to ph7 tx tex a nmi prescaler/ time base timer remocon input fifo serial interface unit (ch1) ch0 ch 1 8 port j pa0/ppo0 to pc2/ppo18 pc3/rto3 to pc7/rto7 fifo programmable prescaler pg5/pck block diagram
?3 CXP81952/81960 pin configuration 1 (top view) 100-pin qfp package pb5/ppo13 pb4/ppo12 pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pi6/so1 pi7/si1 pe0/int0 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0 pg1 pg2 pg3 pg4 pg5/pck pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref av ss pf4/an8 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd v ss tx tex pi1/rmc pi2/pwm pi3/to/adj pi4/int1/nmi pi5/sck1 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 note) 1. nc (pin 90) is always connected to v dd . 2. vss (pins 41 and 88) are both connected to gnd.
?4 CXP81952/81960 pin configuration 2 (top view) 100-pin lqfp package pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0 pg1 pg2 pg3 pg4 pg5/pck pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref pb4/ppo12 pb5/ppo13 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd v ss tx tex pi1/rmc pi2/pwm pi3/to/adj pi4/int1/nmi pi5/sck1 pi6/so1 pi7/si1 pe0/int0 pd2 pd1 pd0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 pf4/an8 av ss 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 76 77 78 79 80 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 note) 1. nc (pin 88) is always connected to v dd . 2. vss (pins 39 and 86) are both connected to gnd.
?5 CXP81952/81960 output/ real time output output/ real time output i/o/ real time output i/o/ real time output i/o input/input input/input/input output/output output/output output/output output/output output/output output/output input input/input output/input i/o ouput input input (port a) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port c) 8-bit i/o port, enables to specify i/o by bit unit. data is gated with ppo or rto contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. enable to specify i/o by 4-bit unit. enables to drive 12ma sink current. (8 pins) (port e) 8-bit port. lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) analog input pins to a/d converter. (12 pins) (port f) lower 4 bits are input port and upper 4 bits are output port. lower 4 bits also serve as standby release input pin. (8 pins) serial clock (ch0) i/o pin. serial data (ch0) output pin. serial data (ch0) input pin. serial chip select (ch0) input pin. external event input pin for timer/counter. input pin to request external interruption. active when falling edge. input pin to request external interruption. active when falling edge. pwm output pins. (2 pins) da gate pulse output pins. (4 pins) programmable pattern generator (ppg) output. functions as high precision real time pulse output port. (19 pins) real time pulse generator (rtg) output. functions as high precision real time pulse output port. (5 pins) symbol i/o description pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0 to pd7 pe0/int0 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 sck0 so0 si0 cs0 pin description
?6 CXP81952/81960 pg0 to pg4 pg5/pck pg6/exi0 pg7/exi1 ph0 to ph7 pi1/rmc pi2/pwm pi3/to/adj pi4/int1/ nmi pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 extal xtal tex tx rst mp av dd av ref avss v dd vss input output i/o/input i/o/output i/o/output/output i/o/input/input i/o/i/o i/o/output i/o/input i/o input output input output input input input 7 bit general purpose prescaler input pin. external input pin to frc capture unit. (port g) 8-bit input port. (8 pins) (port h) 8-bit output port ; medium withstand voltage (12v) and high current (12ma), n-ch open drain output. (8 pins) remote control receiving circuit input pin. 14-bit pwm output pin. timer/counter, 32khz oscillation adjustment output pin. input pin to request external interruption and non-maskable interruption. active when falling edge. serial clock (ch1) i/o pin. serial data (ch1) output pin. serial data (ch1) input pin. (port i) 7-bit i/o port. i/o port can be specified by bit unit. (7 pins) (port j) 8-bit i/o port. function as standby release input can be specified by bit unit. i/o can be specified by bit unit. connecting pin of crystal oscillator for system clock. when supplying the external clock, input the external clock to extal pin and input opposite phase clock to xtal pin. connecting pin of crystal oscillator for 32khz timer clock. when used as event counter, input to tex pin and leave tx pin open. (feedback resistor is not removed.) system reset pin of active "l" level. microprocessor mode input pin. always connect to gnd. positive power supply pin of a/d converter. reference voltage input pin of a/d converter. gnd pin of a/d converter. positive power supply pin. gnd pin. connect both vss pins to gnd. symbol i/o description
?7 CXP81952/81960 ppo, rto data data bus rd (port c) aaaa aaaa aa aa port c direction aaaa aaaa port c data input protection circuit ip (every bit) aa aa data bus rd (port d) aaaa aaaa aa aa port d direction aaaa aaaa port d data high current 12ma ip (every 4 bits) aa aa pd0 to 3 pd4 to 7 16 pins hi-z hi-z when reset pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 hi-z pd0 to pd7 aaaa aaaa aa aa ppo data data bus output becomes active from high impedance by data writing to port register. port a or port b rd input/output circuit formats for pins port a port b pin circuit format 8 pins 8 pins port c port d
?8 CXP81952/81960 aa ip aa aa data bus rd (port e) input protection circuit interruption circuit/ event counter 1 pin hi-z hi-z when reset pe0/int0 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 hi-z h level rd aa ip aa aa data bus input protection circuit interruption circuit port e port e pin circuit format 1 pin data bus rd (port e) aaaa aaaa aa aa aa aa aa aa da gate output or pwm output hi-z control mpx aaaa aaaa port e data port/da output select data bus rd (port e) aaaa aaaa aa aa aaa a a a aaa da gate output hi-z control mpx aaaa aaaa port e data port/da output select port e 4 pins pe6/dab0 pe7/dab1 2 pins port e
?9 CXP81952/81960 rd (port f) data bus aa aa aa aa ip input multiplexer a/d converter 4 pins hi-z hi-z when reset an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 hi-z hi-z aa aa aa aa ip a/d converter input multiplexer port f pin circuit format 4 pins a/d converter data bus rd (port f) aaaa a port/ad select ip aa aa aaaa aaaa port f data input multiplexer aa aa a ip rd (port g) data bus schmitt input pg5: to general purpose prescaler port f 4 pins pg0 to pg4 pg5/pck 8 pins port g hi-z aa aa a ip rd (port g) data bus schmitt input frc capture unit 6 pins pg6/exi0 pg7/exi1 port g hi-z data bus rd (port h) aa aa aaa aaa port h data large current 12ma medium withstand voltage 12v 2 pins ph0 to ph7 port h
?10 CXP81952/81960 hi-z pin when reset circuit format pi2/pwm pi3/to/adj 2 pins 3 pins hi-z hi-z pi1/rmc pi4/int1/nmi pi7/si1 aa aa pi1: to remote control circuit pi4: to interruption circuit pi7: to serial ch1 aaaa port i data aa aa ip data bus rd (port i) aaaa aaaa port i direction schmitt input aa aa aaa a a a a a a aaa pi2: from 14-bit pwm pi3: from timer/counter, 32khz timer mpx aaaa aaaa port i data aa aa ip data bus rd (port i) aaaa aaaa port i direction aaaa aaaa port i function select port i pi5/sck1 pi6/so1 aa aaa a a a aaa mpx aaaa aaaa port i data a ip data bus rd (port i) aaaa aaaa port i direction aaaa aaaa port i function select aa aa aa aa mpx to serial ch1 note) pi5 is schmitt input pi6 is inverter input from serial ch1 2 pins port i port i
?11 CXP81952/81960 so0 output enable aa aa so0 from sio pin when reset circuit format 8 pins 1 pin hi-z hi-z hi-z pj0 to pj7 aa aa standby release aaaa aaaa port j data a a ip data bus rd (port j) aaaa aaaa port j direction aa aa edge detection data bus rd port j cs0 si0 aa aa aa ip schmitt input to sio 2 pins so0 2 pins oscillation extal xtal aa aa ip aa aa extal xtal ?shows the circuit composition during oscillation. ?feedback resistor is removed during stop. 1 pin hi-z sck0 sck0 output enable aa aa internal serial clock from sio aa aa ip schmitt input external serial clock to sio
?12 CXP81952/81960 pin when reset circuit format 2 pins oscillation tex tx aa aa aa aa ip aa aa tex tx ?shows the circuit composition during oscillation. ?feedback resistor is removed during 32khz oscillation circuit stop by software. at this time tex pin outputs "l" level and tx pin outputs "h" level. 32khz timer counter 1 pin hi-z mp aa aa aa aa ip cpu mode 1 pin l level rst aa a ip schmitt input pull-up resistor mask option op
?13 CXP81952/81960 * 1 av dd and v dd should be set to a same voltage. * 2 v in and v out should not exceed v dd + 0.3v. * 3 the large current operation transistors are the n-ch transistors of the pd and ph ports. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium withstand output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d low level output current ?.3 to +7.0 avss to +7.0 * 1 ?.3 to +0.3 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ?.3 to +15.0 ? ?0 15 20 130 ?0 to +75 ?5 to +150 600 380 v v v v v v ma ma ma ma ma ? ? mw ph pin total of output pins other than large current output pins: per pin large current port pin * 3 : per pin total of output pins qfp package type lqfp package type item symbol rating unit remarks absolute maximum ratings (vss = 0v)
?14 CXP81952/81960 analog power supply high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 5.5 v dd v dd 5.5 v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.4 0.2 +75 v v v v v v v v v v v v v v v ? item symbol min. max. unit remarks 3.0 2.7 2.7 2.0 3.0 0.7v dd 0.8v dd v dd ?0.4 v dd ?0.2 0 0 0 ?.3 ?.3 ?0 av dd v ih v ihs v ihex v il v ils v ilex topr guaranteed range during high speed mode (1/2 dividing clock) operation guaranteed range during low speed mode (1/16 dividing clock) operation guaranteed operation range by tex clock guaranteed data hold operation range during stop * 1 * 2 cmos schmitt input * 3 and pe0/int0 pin cmos schmitt input * 6 extal pin * 4 , * 7 and tex pin * 5 , * 7 extal pin * 4 , * 8 and tex pin * 5 , * 8 * 2 , * 7 * 2 , * 8 cmos schmitt input * 3 and pe0/int0 pin extal pin * 4 , * 7 and tex pin * 5 , * 7 extal pin * 4 , * 8 and tex pin * 5 , * 8 v dd * 1 av dd and v dd should be set to a same voltage. * 2 normal input port (each pin of pc, pd, pf0 to pf3, pg, pi and pj), mp pin. * 3 each pin of sck0, rst, pe1/ec/int2, pi1/rmc, pi4/int1/nmi, pi5/sck1 and pi7/si1. * 4 it specifies only when the external clock is input. * 5 it specifies only when the external event count clock is input. * 6 each pin of cs0, si0, and pg. * 7 in case of 4.5 to 5.5v supply voltage (v dd ). * 8 in case of 3.0 to 3.6v supply voltage (v dd ). recommended operating conditions (vss = 0v)
?15 CXP81952/81960 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 v v v v v ? ? ? ? ? ? ? pd, ph pa to pd, pe2 to pe7, pf4 to pf7, ph (v ol only) pi1 to pi7 pj, so0, sck0 extal tex rst * 1 item symbol pins conditions min. other than v dd , vss, av dd , and avss clock 1mhz 0v other than the measured pins v dd i dd1 i iz i loh i dds1 i dd2 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?0 50 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = ?0 to +75?, vss = 0v) * 1 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. * 2 when entire output pins are open. * 3 when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00fe h ) to "00" and operating in high speed mode (1/2 dividing clock). v dd = 5v 0.5v * 3 sleep mode v dd = 5v 0.5v v dd = 5v 0.5v supply current * 2 input capacity v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v v oh = 12v 16mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current (n-ch tr off in state) pa to pg, pi, pj, mp an0 to an3, cs0, si0, so0 sck0, rst * 1 ph 31 2.0 46 9 10 50 8 110 35 10 20 ma ma ? ? ? pf v dd = 3v 0.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf)
?16 CXP81952/81960 v dd = 3.0v, i oh = ?.15ma v dd = 3.0v, i oh = 0.5ma v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v ih = 3.6v high level output voltage 2.7 2.3 0.3 ?.3 0.1 ?.1 ?.9 v v v v v ? ? ? ? ? ? ? pd, ph pa to pd, pe2 to pe7, pf4 to pf7, ph (v ol only) pi1 to pi7 pj, so0, sck0 extal tex rst * 1 item symbol pins conditions min. other than v dd , vss, av dd , and avss clock 1mhz 0v other than the measured pins v dd i dd1 i iz i loh i dds1 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.3 0.5 1.0 20 ?0 10 ?0 ?00 ?0 50 max. unit dc characteristics (v dd = 3.0 to 3.6v) (ta = ?0 to +75?, vss = 0v) * 1 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. * 2 when entire output pins are open. * 3 when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00fe h ) to "00" and operating in high speed mode (1/2 dividing clock). v dd = 3.3v 0.3v * 3 sleep mode v dd = 3.3v 0.3v v dd = 3.3v 0.3v supply current * 2 input capacity v dd = 3.6v, v il = 0.3v v dd = 3.6v, v i = 0, 3.6v v dd = 3.6v, v oh = 12v 12mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current pa to pg, pi, pj, mp an0 to an3, cs0, si0, so0 sck0, rst * 1 ph 15 0.8 10 30 2.5 10 20 ma ma ? pf
?17 CXP81952/81960 fig. 1, fig. 2 fig. 1, fig. 2 (external clock drive) fig. 1, fig. 2 (external clock drive) fig. 3 fig. 3 fig. 2 v dd = 2.7 to 5.5v (32khz clock applied condition) fig. 3 fig. 3 * t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") extal t xh t xl t cf t cr 0.4v v dd ?0.4v 1/fc aaaa a aa a aaaa external clock extal xtal 74hc04 aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count clock input pulse width event count clock input rise and fall times system clock frequency event count clock input pulse width event count clock input rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal xtal extal xtal extal ec ec tex tx tex tex mhz ns ns ns ns khz ? ms item symbol pins conditions unit min. 1 1 28 37.5 t sys 4 * 32.768 10 max. 16 12 200 20 20 (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) fig. 1. clock timing fig. 2. clock applied condition tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
?18 CXP81952/81960 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) cs, sck, si and so means each pin of cs ? cs0, sck ? sck0, si ? si0, and so ? so0 respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) item cs ? sck delay time cs -? sck floating delay time cs ? so delay time cs ? so floating delay time cs high level width sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 100 8000/fc ?100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 200 100 max. unit condition
?19 CXP81952/81960 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) cs, sck, si and so means each pin of cs ? cs0, sck ? sck0, si ? si0, and so ? so0 respectively. note 3) the load of sck output mode and so output delay time is 50pf. serial transfer (ch0) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v) item cs ? sck delay time cs -? sck floating delay time cs ? so delay time cs ? so floating delay time cs high level width sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 250 t sys + 200 t sys + 250 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 100 8000/fc ?150 t sys+100 200 2 t sys+100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 250 125 max. unit condition
?20 CXP81952/81960 fig. 4. serial transfer timing (ch0) cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
?21 CXP81952/81960 serial transfer (ch1) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) item symbol pin min. max. unit condition sck1 cycle time sck1 high and low level widths si1 input setup time (against sck1 - ) si1 input hold time (against sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 2 t sys + 200 8000/fc t sys + 100 4000/fc ?100 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. serial transfer (ch1) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v) item symbol pin min. max. unit condition sck1 cycle time sck1 high and low level widths si1 input setup time (against sck1 - ) si1 input hold time (against sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 2 t sys + 200 8000/fc t sys + 100 4000/fc ?150 100 200 t sys + 200 100 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck1 output mode and so1 output delay time is 50pf.
?22 CXP81952/81960 external clock input frequency external clock input pulse width external clock input rise and fall times f pck t wh , t wl t r , t f pck pck pck 33 12 200 mhz ns ns item symbol pin condition min. typ. max. unit (3) general purpose prescaler (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) 1/f pck t f t wh 0.8v dd t r t wl 0.5v dd 0.2v dd pck fig. 6. general purpose prescaler timing fig. 5. serial transfer ch1 timing sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
?23 CXP81952/81960 conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian i ref ta = 25? v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode linearity error absolute error resolution av ref current av ref i refs ? ? v v av dd 1.0 ma 10 a 0.6 160/f adc * 12/f adc * av dd ?0.5 0 item symbol pins conditions min. typ. max. unit bits (4) a/d converter characteristics (ta = ?0 to +75?, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v) 8 ? ? lsb lsb analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value * the value of f adc is as follows by selecting adc operation clock (msc: address 01ff h bit 0). when ps2 is selected, f adc = fc/2 when ps1 is selected, f adc = fc fig. 7. definitions of a/d converter terms conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian i ref ta = 25? v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode linearity error absolute error resolution av ref current av ref i refs ? ? v av dd 0.7 ma 10 ? 0.4 160/f adc * 12/f adc * av dd ?0.3 0 item symbol pins conditions min. typ. max. unit bits (ta = ?0 to +75?, v dd = av dd = 3.0 to 3.6v, av ref = 2.7 to av dd , vss = av ss = 0v) 8 ? ? lsb lsb v dd = av dd = 3.0 to 3.6v av ref an0 to an11 av ref v dd = av dd = 4.5 to 5.5v an0 to an11
?24 CXP81952/81960 external interruption high and low level widths reset input low level width int0 int1 int2 nmi pj0 to pj7 rst 1 32/fc ? ? item symbol pins conditions min. max. unit t ih t il t rsl (5) interruption, reset input (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 int1 int2 nmi pj0 to pj7 (during standby release input) (falling edge) fig. 8. interruption input timing t rsl 0.2v dd rst fig. 9. reset input timing (6) others (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) item exi input high and low level widths t eih t eil exi0 exi1 ns symbol pins min. t frc 8 + 200 + t sys max. unit t sys = 2000/fc conditions note) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") t frc = 1000/fc [ns] 0.8v dd exi0 exi1 t eih t eil 0.2v dd fig. 10. other timings
?25 CXP81952/81960 supplement fig. 11. recommended oscillation circuit aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd (i) aaaaa a aaa a aaaaa tex tx c 1 c 2 rd (ii) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 12.00 12 12 30 18 470k (ii) 32.768khz 10 5 16 (12) 10 16.00 5 16 (12) 16 (12) 0 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (i) item content reset pin pull-up resistor non-existent existent mask option table 16.00 12 12 16 (12)
?26 CXP81952/81960 characteristics curve (100a) 3 45 6 0.1 5.0 1.0 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 0 30 20 10 510 16 40 (100a) 3 45 6 0.1 5.0 1.0 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 0 30 20 10 51015 40 1 v dd ?supply voltage [v] i dd ?supply current [ma] i dd vs. v dd (fc = 16mhz, ta = 25?, typical) 1/16 dividing mode sleep mode 32khz mode (instruction) 32khz sleep mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode frequency [mhz] i dd ?supply current [ma] i dd vs. fc (v dd = 5v, ta = 25?, typical) 1/2 dividing mode 1/4 dividing mode v dd ?supply voltage [v] i dd ?supply current [ma] i dd vs. v dd (fc = 12mhz, ta = 25?, typical) 1/16 dividing mode sleep mode 1/2 dividing mode 1/4 dividing mode frequency [mhz] i dd ?supply current [ma] i dd vs. fc (v dd = 3.3v, ta = 25?, typical) 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode
?27 CXP81952/81960 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g sony code eiaj code jedec code package material lead treatment lead material package weight epoxy/phenol resin solder plating 42 alloy package structure detail a lqfp-100p-l01 * qfp100-p-1414-a 100pin lqfp (plastic) 16.0 0.2 * 14.0 0.1 75 51 50 26 25 1 76 0.5 0.08 0.18 ?0.03 + 0.08 (0.22) a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (15.0) 0?to 10 0.1 0.1 0.5 0.2 100 0.1 note: dimension * ?does not include mold protrusion.

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